The present disclosure relates to an interconnect structure in a semiconductor packaging.
Three-dimensional (3D) stacked substrate arrangements are electronic devices having a plurality of stacked semiconductor die/chips/wafers that are physically and electrically interconnected with one another. Package on package (PoP) is particularly an integrated circuit packaging method to combine vertically discrete logic through various interconnection structures. Two or more packages are installed atop each other with an interconnection interface to route signals between them. This allows higher component density in devices, such as mobile phones, personal digital assistants (PDA), and digital cameras.
Electrically, PoP offers benefits by minimizing track length between different interoperating parts, such as a controller and a memory. This yields better electrical performance of devices, since shorter routing of interconnections between circuits yields faster signal propagation and reduced noise and cross-talk.
With each generation, as devices operate at lower voltages and higher frequencies, current levels at the die-to-die and/or at the die-to-package interconnection interface are increasing. The maximum allowable current density of widely used solder interconnects is seriously challenged in the ball-grid array (BGA) package setting.